Like many other kinds of integrated circuits (IC's), those with programmable types of interconnect have historically continued to grow in terms of circuit density and complexity. Signal-processing speed has also tended to increase. As a result, the following attributes have become areas of growing concern: the robustness of the programmable interconnect, its ability to avoid signal traffic congestion, and its ability to avoid excessive consumptions of electrical power at localized points (e.g., due to high frequency driving of high capacitance loads).
Typically, designers try to throw in larger numbers of “general interconnect” lines and greater varieties of such into the programmable routing resources of FPGA's in order to try to assure that the various programmable logic sections (e.g., CLB's or Configurable Logic Blocks) in the IC will be able to acquire a wide variety of input signals and/or deliver respective output signals from/to other such CLB's and/or from/to I/O Blocks (IOB's) in timely and deterministic fashion; this being done so that appropriate communication can take place between such spaced-apart logic or other sections of the IC as may be required for programmably implementing desired logic functions. “General interconnect” lines are those which are not dedicated for use only by specific drive circuits or are not dedicated for specific functions (e.g., carrying memory address signals). Such general interconnect lines can be assigned by place-and-route software for use by any of a multitude of signal sources and/or for any of a multitude of functions.
The brute force solution of simply adding more and more general interconnect lines of different lengths and orientations into a programmable IC is all well and good. However, as circuit and interconnect densities grow it becomes more difficult to make efficient use of circuit resources while at the same time comporting with limitations on power consumption. For example, it may not be wise to drive a high frequency signal onto a relatively long gi-line (a general interconnect line with relatively large electrical capacitance) merely to couple the signal from one CLB to an immediately adjacent CLB. A shorter interconnect line may be more efficient. Most of the circuit space consumed by the length of the relatively long gi-line (e.g., an octal length line) will be wasted. Also, energy will be wasted in driving the greater capacitance of the long gi-line at high frequency. On the other hand, if there are too many relatively short gi-lines (e.g., those with a length of say, one CLB tile; defined as 1×CL below) then a large signal propagation time may be disadvantageously incurred if a signal has to be transported a relatively long distance by use of such short-haul gi-lines. The delay will be due to the many routing switches that are disposed along the way for provided programmable routing from each short gi-line (e.g., 1×CL) to the next. Aside from loading the routing lines, the many routing switches disadvantageously consume circuit space which might otherwise be used for providing higher logic density.
It is difficult to find a correct balance of interconnect resources. It is difficult to determine what mix of long-haul and short-haul gi-lines will efficiently implement all different kinds of designs that are to be programmably implemented in an FPGA.
Practitioners skilled in the art of once-programmable or re-programmable logic arrays such as Field Programmable Gate Arrays (FPGA's) have come to recognize the benefits of using a varied-granularity of interconnects wherein conductors of differing lengths (e.g., double-length, quad-length, etc.) are used, and where the conductors may further be of differing orientations, and where the types of interconnect may have other differing attributes (including differing drive capabilities such as tristateable, or not) in accordance with concepts introduced for example, in U.S. Pat. No. 5,185,706 issued Feb. 9, 1993 to Om P. Agrawal et al. To some extent, the growing lists of different kinds of interconnect (e.g., short-haul general interconnect, medium-haul general interconnect, long-haul general interconnect, dedicated non-general interconnect, etc.) has become a curse. Place-and-route software has to contend with a growing list of different kinds of interconnect and different navigation options available for each kind of interconnect resource at each position in the programmable circuitry. This creates a scalability problem.